As is known and shown by way of example in FIG. 1, a flash memory array 1 comprises a plurality of flash cells 2 disposed in rows and columns, wherein the gate terminals of the cells 2 disposed in a same row are connected to a respective word line 3, the drain terminals of the cells 2 disposed in a same column are connected to a respective bit line 4 and the source terminals are generally connected to ground. The word lines 3 are connected to a row decoder 5 and the bit lines 4 are connected to a column decoder 6 which receive respective address and control signals from a control unit 7 which enables the selection, each time, of a single word line 3 and a single bit line 4 and thus access to the cell 2 connected to the word line and the selected bit line.
A cell 2 may in particular be read by connecting the selected word line 3 to an external voltage V.sub.CPX of predetermined value (for instance 8-9 V) and by forcing a bias current I.sub.f into the selected bit line 4. Maintaining the selected cell in the linear region, the following equation is valid: EQU I.sub.f =K* (W/L)*[(V.sub.CFX -V.sub.th)-V.sub.DS /2]*V.sub.DS(1)
in which K is a constant connected with the manufacturing process, W/L is the width/length dimensional relationship of the cell, V.sub.th is the threshold voltage of the cell (i.e., the minimum voltage to be applied between the gate and source terminals of this cell so that it starts to conduct current) and V.sub.DS is the drain-source drop of the cell. In (1), the term K*(W/L)*V.sub.DS =GM.sub.f represents the transconductance (gain) of the cell and the term (V.sub.CPX -V.sub.th) represents the overdrive of the cell.
By appropriately biasing the cell, the drop V.sub.DS is constant and the term V.sub.DS /2 is negligible with respect to the overdrive (V.sub.CPX -V.sub.th); in this condition the current I.sub.f flowing through the cell depends in a linear manner on the threshold voltage V.sub.th.
During writing, the cell is selected by biasing the connected bit and word lines to respective predetermined programming voltage values. Writing takes place by means of the hot electron injection phenomenon, on the basis of which the high voltage supplied to the drain terminal of the cell to be written causes an increase in the velocity of the electrons and some of these achieve an energy sufficient to overcome the oxide barrier. By forcing a voltage on the gate terminal that is higher than the voltage at the drain terminal, the obtained electric field accelerates the electrons through the oxide layer that separates the channel region from the floating gate region and enables the entrapment of these electrons within the floating gate region. As a result of this entrapment of electrons, the cell modifies its threshold voltage.
The phenomenon of hot electron injection is, by its nature, uncontrolled and cannot be repeated with precision; during programming, the cell is therefore read several times in order to read the achieved threshold voltage (verify phase).
For this reason, an analog memory formed by flash cells has a storage precision that depends on the precision of reading. The threshold voltage is, moreover, highly dependent on the temperature and the manufacturing process used; this means that, in order to obtain a high level of precision and reliability, it is necessary to provide for solutions that ensure substantial insensitivity to variations in operating conditions.
In order to enable high-precision reading of flash memory cells, a preceding European Patent Application 96830612.6 filed on Dec. 5, 1996 in the name of the applicant and entitled "Method and circuit for checking multi-level programming of floating-gate nonvolatile memory cells, particularly flash-cells" discloses a closed-loop circuit in which a current of predetermined value is forced through a first terminal (for instance the drain terminal) of the cell to be read; this first terminal is connected to an input of an operational amplifier that also receives a reference voltage; the second terminal (for instance the source terminal) of the cell is connected to a predetermined potential and the output of the operational amplifier is connected to the gate terminal of the cell. In this way, a voltage directly proportional to the threshold voltage of the cell is present at the output of the operational amplifier and can be compared with the desired threshold voltage in order to decide whether or not to continue programming.
This solution, although precise, raises the problem of the high capacitance associated with the drain terminal of the cell to be read, due to the sum of all the capacitances associated with the cells connected in parallel to the same bit line. This capacitance in effect introduces a pole into the transfer function which slows down the reading. In particular, the maximum speed that can be achieved, in terms of frequency, F.sub.MAX is given by the equation: EQU F.sub.MAX =GM.sub.f /C.sub.p (2)
in which GM.sub.f is the transconductance of the cell, as defined above, and C.sub.p is the capacitance associated with the bit line in question. In (2) GM.sub.f cannot be modified as it depends on design and technology considerations; C.sub.p could be reduced by increasing the voltage applied to the drain terminal of the cell but, in order to avoid the risk of cancellation of the cell, this voltage cannot be excessively increased.